In recent years, digitization of video signal processing and diversification of input sources of television receivers are progressing, and there is employed a clock generation apparatus which synchronizes a reference signal such as a horizontal sync signal of a video signal with a clock for video signal processing.
Hereinafter, a conventional clock generation apparatus will be described.
FIG. 28 is a block diagram illustrating a PLL circuit as a clock generation circuit proposed in Japanese Published Patent Application No. Hei. 5-90958. With reference to FIG. 28, reference numeral 301 denotes a horizontal sync signal input terminal, 302 denotes an analog-to-digital converter (ADC), 303 denotes a master clock (MCK) input terminal, 304 denotes a digital phase comparator, 305 denotes a frequency divider, 306 denotes a digital low-pass filter (LPF), 307 denotes a digital timing oscillator (DTO), 308 denotes a digital-to-analog converter (DAC), 309 denotes an analog phase comparator, 310 denotes a reference (REF) signal input terminal, 311 denotes an analog LPF, 312 denotes an analog VCO, and 313 denotes a clock output terminal.
This PLL circuit is provided with, in addition to a first loop which compares the phase of a horizontal sync signal inputted through the horizontal sync signal input terminal 301 with the phase of a signal based on an output signal of the DTO 307 by the digital phase comparator 304, and controls the DTO 307 with the output of the comparator 304, a second loop which compares the phase of the output signal of the DTO 307 with the phase of an REF signal inputted through the REF signal input terminal 310 by the analog phase comparator 309, and supplies an output of the analog VCO 309 to the clock of the DTO 307 according to the output of the comparator 309, whereby the PLL circuit is operated as a digital PLL as a whole to generate a clock synchronized with the horizontal sync signal that is inputted through the horizontal sync signal input terminal 301.
In the conventional construction, however, the output of the PLL circuit can be synchronized with only a single sync signal. Therefore, if the conventional clock generation circuit is used in a device to which a certain video signal is inputted from among plural kinds of video signals, like a television receiver in recent years, it is impossible to take a response such as generating a burst lock clock for a composite signal like a video signal while generating a line lock clock for a component signal.
Further, when receiving a personal computer signal input, it is necessary to shift the clock phase of the input ADC. However, in the construction of the conventional clock generation circuit, it is impossible to shift the clock phase of the input ADC when receiving such personal computer signal.
Furthermore, although a video signal and a sync signal are separated in the personal computer signal, the conventional clock generation circuit cannot respond to that the video signal and the sync signal are separated.
Moreover, in recent systems, in order to prevent interference due to a high frequency to be used, conscious spread of the frequency or the like is carried out. However, the conventional clock generation circuit cannot take a response such as consciously spreading the frequency.
Furthermore, during a signal processing in a liquid crystal television receiver or the like, it is necessary to generate both a burst clock and a line clock. However, the conventional clock generation circuit cannot generate both of these clocks, and therefore, it cannot be used in a liquid crystal television or the like.